This invention relates to a memory device capable of very large scale integration to provide a memory cell array.
In conventional semiconductor memories, one bit of information is represented by electrons stored in a static capacitor in each memory cell. The binary number xe2x80x9c1xe2x80x9d is represented by a deficit of N electrons and xe2x80x9c0xe2x80x9d is represented by a neutral charge state. In a typical 16 Mbit dynamic random access memory (DRAM), the number of electrons N is around 800,000. In order to increase the memory capacity, the individual memory cells need to be made smaller, but this cannot be achieved simply by scaling down the conventional memory cell because there is a lower limit to the value of N. The number of electrons N is limited by the need to accommodate leakage current from the cell, internal noise and the effect of incident alpha particles, and these factors do not reduce commensurately with a reduction in the area of the memory cell. It can be estimated that N must be in excess of 130,000 in a 16 Gbit DRAM i.e a factor of approximately 6 times less than for a 16 Mbit DRAM. However, the cell size required for a 16 Gbit DRAM needs to reduce by the factor of three orders of magnitude as compared with a 16 Mbit DRAM and consequently, the reduced cell size cannot accommodate the number of electrons required for satisfactory operation. In an attempt to maintain the value of N sufficiently large, three dimensional capacitors with trench or stacked structures, together with high dielectric capacitor films have been investigated but the resulting proposed structures and fabrication processes become extremely complicated. Furthermore, the power consumption increases significantly because the relatively large number N of electrons in the cells need to be refreshed within a storage time which tends to become shorter as the scale of the device is miniaturised.
Another type of memory device is known as a flash memory, which exhibits non-volatile characteristics. In such a device, approximately 105 electrons are injected into a floating gate through a tunnelling barrier, typically formed of SiO2 with a thickness of the order of 10 nm. The stored charge produces a field which influences current flow in a source-drain path. Charge is either written to or erased from the floating gate by application of an electric field through a control gate. A relatively high electric field is applied during the erase and write cycles and as a result the SiO2 film is degraded, limiting the life of the memory to a predetermined number of erase/write cycles, typically of the order of 105 cycles. Furthermore, the erase/write times are typically several milliseconds, four orders of magnitude slower than that of a conventional DRAM. Such poor performance limits the application of flash memory devices.
Hitherto, alternative approaches have been proposed to provide memory devices which operate with small, precise numbers of electrons, known as single electron memory devices. A single electron memory device is described in our PCT/GB93/02581 (WO-A-94/15340). A precise number of electrons enter or leave a memory node through a multiple tunnel junction under the control of applied gate voltages and the electron state at the memory node is detected by means of an electrometer. However, a disadvantage of the device is that a significant amount of circuitry is required for each memory node and the device currently operates only at low temperature, below the liquid helium temperature of 4.2K. Another single electron memory device has been proposed and demonstrated by K. Yano, T. Ishii, T. Hashimoto, T. Kobayasi, F. Murai and K. Seki in IEEE Transactions on Electron Devices, September 1994, Vol. 41, No. 9, pp. 1628-1638, and by K. Yano, T. Ishii, T. Sano, T. Mine, F. Murai and K. Seki in 1996 IEEE International Solid-State Circuits Conference, 1996, FP 16.4, p. 266. The device utilises a polycrystalline film extending between a source and drain, to which a gate voltage is applied. A small number of electrons is stored in the granular structure of the polycrystalline silicon film. The memory size is relatively small as compared with the structure in PCT/GB93/02581 supra and is operable at room temperature. Furthermore, the memory shows several advantages as compared with conventional flash memory, with a faster erase/write time due to the small number of stored electrons, and the operational lifetime is improved because low-voltage tunnel injection is utilised rather than high-field electron injection. However, the time to read stored information is relatively long, of the order of several microseconds, because the resistance between the source and drain needs to be sufficiently high to ensure long storage time of electrons in the grains.
Another structure is described by S. Tiwari, F. Rana, H. Hanafi, A. Hartstein, E. F. Crabbe and K. Chan in Applied Physics Letters, 4 Mar. 1996, Vol 68, No. 10, pp. 1377-1379, by S. Tiwari, F. Rana, K. Chan, L. Shi and H. Hanafi in Applied Physics Letters, 26 Aug. 1996, Vol 69, No. 9, pp. 1232-1234, and H. I. Hanafi, S. Tiwari and I. Khan in IEEE Transactions on Electron Devices, 9 Sep. 1996, Vol 43, No. 9, pp 1553-1558. This memory device utilises silicon-crystals that underlie the gate of a transistor device. Electrons are injected into the silicon nano-crystals, which are 5 nm in dimension, from the silicon substrate through a thin tunnelling oxide layer of the order of 1.1-1.8 nm thickness. Stored electrons shift the threshold voltage of the transistor. The time to read stored information is relatively short, of the order of several tens of nanoseconds, because the transistor channel has a high electron mobility. The endurance cycle for writing and erasing information is significantly improved relative to a conventional flash memory device. However, the erase time is unsatisfactorily long, of the order of several milliseconds because the conduction band alignment is unfavourable for electrons to tunnel from the nano-crystals into the bulk silicon.
Another memory device which operates according to the principles of flash memory is disclosed in Electrically-Alterable Memory Using a Dual Electron Injector Structure, D. J. DiM aria, K. M. DeMeyer and D. W. Dong, IEEE Electron Device Letters, Vol. EDL-1, No.9, September 1980, pp.179-181. In this device, the conductivity of the source/drain path is controlled by charge written or erased from a floating gate through a tunnelling barrier from a gate electrode. However, disadvantages of this device are that it has a slow writing/erasing time, of the order of milliseconds, and that the life of the tunnel barrier is limited because Fowler-Nordheim high field injection is used as in a conventional flash memory. A similar device is described in U.S. Pat. No. 3,878,549 to S. Yamazaki
With a view to overcoming these problems and disadvantages the invention provides a memory device comprising a path for charge carriers, a node for storing charge to produce a field which alters the conductivity of the path, and a tunnel barrier configuration through which charge carriers tunnel in response to a given voltage so as to become stored on the node, the tunnel barrier configuration exhibiting an energy band profile that comprises a dimensionally relatively wide barrier component with a relatively low barrier height, and at least one dimensionally relatively narrow barrier component with a relatively high barrier height.
The invention permits the writing, reading and erasing times for the memory device all to be optimised.
The relatively wide barrier component of the energy band profile acts as a barrier for long term storage of charge on the node. The wide barrier component can be raised and lowered selectively so that charge can then tunnel through the relatively narrow barrier component so as to be written onto or erased from the node.
The component of the energy band profile that has a relatively high barrier height may be provided by an element with a width of 3 nm or less. A plurality of the relatively high barrier components may be included and may conveniently provide a multiple tunnel junction configuration.
The barrier configuration may be fabricated in a number of different ways. It may include alternate layers of relatively electrically conductive and insulating material, in which the layers collectively provide the relatively wide, low barrier height component of the energy band profile, and the individual insulating layers provide the relatively high barrier components. The alternate layers may comprise polysilicon and silicon nitride respectively although other materials may be used.
Alternatively, the barrier configuration may comprise a Schottky barrier configuration with alternate layers of electrically conductive material and semiconductor material.
The charge storage node may comprise a layer of electrically conductive material between the barrier configuration and the path. The node may comprise a plurality of conductive islands. In an alternative arrangement, the islands are distributed in the barrier configuration and may give rise to the relatively low barrier components of the energy band profile by virtue of their charging energy. The islands may have a diameter of 5 nm or less. They may be arranged in layers separated by insulating material.
The islands may be formed in a number of different ways. They may comprise nano-crystals of semiconductor material. Alternatively they may be formed of metal, for example by sputtering, so as to distribute them in an insulating metallic oxide. Alternatively, the islands may comprise particles deposited from a liquid suspension of metal or semiconductor particles.
The tunnel barrier configuration may be disposed between the path and a control electrode so that by changing the voltage on the control electrode, the amount of charge that tunnels to the charge storage node can be controlled. In another configuration according to the invention, a gate electrode is provided to apply an additional field to the charge barrier configuration in order to control charge tunnelling to the node.
The amount of charge that can be stored at the node may be limited by the Coulomb blockade effect, to a discrete number of electrons.
In use, the tunnel barrier configuration exhibits a blocking voltage range in which charge carrier tunnelling to the node is blocked, and control means may be provided to increase and decrease the blocking voltage range to control the amount of charge stored in the node. The amount of charge that can be stored at the node may be limited to a plurality of discrete electron states. The control means may be operative to raise and lower the blocking voltage range so as to permit only a selected one of the states to exist at the node.
Alternatively, the control means may be operative to vary the width of the voltage blocking range.
The memory device according to the invention is suited to be manufactured as a plurality of memory cells in an array of rows and columns in a common substrate.
Data may be selectively read from each cell individually, and new data may be written to the cell or the stored data may be refreshed. The memory cell array may include sensing lines for detecting current flowing in the paths of respective columns of the memory cells, word lines, data lines for controlling the barrier configurations of the memory cells of a respective column thereof, a precharge circuit for precharging the sensing lines, the sensing lines taking up a charge level dependent upon the stored charge at the charge storage node of a particular one of the cells in a column thereof read in response to a read voltage applied to a corresponding word line, a read/write circuit for transferring the voltage level of the sensing line to the corresponding word line for the column, a data output responsive to the voltage level on the data line for providing output data corresponding to the stored data in the read cell, and data refreshing means for applying a write voltage to the word line of the read cell such that data corresponding to the voltage level on the data line is written back into the previously read cell. The array may also include means for changing the level of voltage on the data line after operation of the read/write circuit in response to input data to be written into the cell, such that the input data is written to the cell.
Peripheral circuits for the array may be formed on a common substrate with the memory cells, and the source and drains of transistors in the peripheral circuits may be formed by the same process steps that are used to form source and drain regions in the cells of the array.

The invention also includes a method of fabricating a memory device which includes a path for charge carriers, a node for storing charge that alters the conductivity of the path, and a tunnel barrier configuration through which charge carriers tunnel in response to a given voltage so as to become stored on the node, the method including forming the tunnel barrier configuration such that it exhibits an energy band profile that comprises a dimensionally relatively wide barrier component with a relatively barrier height, and at least one dimensionally relatively narrow barrier component with a relatively high barrier height.